Typically, very fast high current output buffers are desired in logic circuits to drive a subsequent stage. The high current output of the buffer is necessary to quickly change the state of any subsequent stage since, if a subsequent stage has an inherent input capacitance, the capacitance must first be adequately charged to switch the subsequent stage. Total load capacitance may result from the capacitance of interconnect lines and/or the capacitance of the subsequent stage itself. For example, if the input device of a subsequent stage is a MOSFET, sufficient charge must first be applied to the gate of the MOSFET in order to turn on the MOSFET. Thus, an output buffer must quickly provide this charge to the gate of the MOSFET. This problem with capacitance also exists with devices incorporating diodes, which have a small inherent capacitance.
Further, even if the effect of the capacitance of a subsequent stage is neglected, the output voltage of the buffer must still first rise to a certain minimum voltage to switch the subsequent stage. As an example, if the input to the subsequent stage is a diode, or other voltage clamping device, coupled to ground, the output buffer must first rise to a voltage equal to the voltage drop of the clamping device in order to switch the subsequent stage. The current provided by the output buffer to cause the desired voltage drop is typically greater than necessary to maintain the desired voltage drop since, to provide fast switching, high current transistors are used in the output buffer. If the clamping device is a diode, once the current provided to the diode has risen sufficiently to drop about 0.7 volts across the diode, any higher level of current provided by the output buffer through the clamping diodes is wasted as heat. This is inefficient, yet being done in the prior art.
Frequently, a clamped voltage is desired as an input into a subsequent stage to limit voltage swing. This can result in improved switching speed and lower dynamic power consumption. Therefore, the problem discussed above with respect to clamped voltages can be encountered in the prior art even if the input of the subsequent stage does not inherently clamp the signal.
The problem of wasted current also occurs if the input device of the subsequent stage is a gallium arsenide (GaAs) MESFET. A simple GaAs MESFET is shown in FIG. 1, wherein an undoped GaAs substrate 10 has a top N- layer 12 having formed in it N+ source region 14 and N+ drain region 16. On the top surface of the device between source region 14 and drain region 16 is formed a Schottky metal contact 18 which forms a Schottky diode with N- layer 12. In order to prevent current from flowing between source region 14 and drain region 16, the Schottky diode is reverse biased, causing a depletion region 20 to extend down into N- layer 12, eventually cutting off all current between source region 14 and drain region 16.
Since, typically, source region 14 is connected to ground potential and drain region 16 is at a positive voltage, any voltage applied to Schottky metal 18 above about 0.5 volts in order to fully turn on the MESFET will cause the Schottky diode to be forward biased with respect to source region 14. Therefore some current will flow through the Schottky diode when the MESFET is biased in its on state. The inherent Schottky diodes in the MESFET are shown within N- layer 12.
Thus, the problems discussed above with respect to the input of the subsequent gate being a diode are also present when the input into the subsequent stage is a GaAs MESFET device. That is, once sufficient voltage has been provided to the Schottky metal 18 to reduce the depletion region in N- layer 12 in order to bias the GaAs MESFET in its on state, the output buffer continues to supply a wasteful high current through the Schottky diode. The prior art output buffer designers have deemed it a desirable tradeoff to continue to supply this high current output to switch the MESFET because of the fast switching obtained.
Typically, a low power input signal is applied to the input of the output buffer, where the low power input signal is not sufficient to provide the desired fast switching response of the subsequent stage.
FIG. 2 shows representative output buffer 30 used in the prior art. Inverter 32 is shown coupled to output buffer 30 to cause transistors Q3 and Q4 of output buffer 30 to be in opposite states. In FIG. 2, depletion type FET transistor Ql is coupled in series with transistor Q2 between supply voltage V.sub.s and ground. The gate of transistor Ql is coupled to its source, and the gate of transistor Q2 is coupled to input signal V.sub.in. V.sub.in is also coupled to the gate of transistor Q4. The common terminals of transistors Ql and Q2 are coupled to the gate of transistor Q3. Transistors Q2 and Q3 are also coupled in series between supply voltage V.sub.s and ground. Output voltage V.sub.out is taken from the common terminals of transistors Q3 and Q4.
The operation of the buffer of FIG. 2 is as follows. As a starting state, assume V.sub.in is high and output voltage V.sub.out is low. Assuming the input device of a subsequent stage, coupled to V.sub.out, is an N-channel device, the subsequent stage input device will not be switched on since V.sub.out is low. When V.sub.in changes to a low state, transistor Q2 will be turned off, allowing the source and gate of transistor Ql to rise to a high voltage. The low V.sub.in voltage also being applied to the gate of transistor Q4 will cause transistor Q4 to be switched off, while the high voltage applied to the gate of transistor Q3 will cause transistor Q3 to conduct. Thus, V.sub.out is pulled up to near the supply voltage V.sub.s, and a high current can now flow through transistor Q3.
When the high voltage V.sub.out is applied to the input device of a subsequent stage, and the input device of the subsequent stage is a clamping type load such as a diode or MESFET load, such as the GaAs MESFET of FIG. 1, a relatively high current is continuously being fed to the clamping load. This high current, as previously discussed, is more than what is necessary to maintain the desired voltage across the clamping load. This wasted current may be manifested as heat which must be controlled so as to not have deleterious effects on the various electrical components.
In inverter 32 of FIG. 2, transistors Ql and Q2 are typically small to conserve surface area, and transistors Q3 and Q4 are large to provide the desired fast switching and high current to the subsequent stage.